/**
 * @copyright 2018 indie Semiconductor
 *
 * This file is proprietary to indie Semiconductor.
 * All rights reserved. Reproduction or distribution, in whole
 * or in part, is forbidden except by express written permission
 * of indie Semiconductor.
 *
 * @file adc_sfr.h
 */

#ifndef __ADC_SFR_H__
#define __ADC_SFR_H__

#include <stdint.h>

/* -------  Start of section using anonymous unions and disabling warnings  ------- */
#if   defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/**
 * @brief A structure to represent Special Function Registers for ADC.
 */
typedef struct {

  union {
    struct {
      uint8_t  ENA                      :  1; /*!< ADC Enable */
      uint8_t  MODE                     :  1; /*!< ADC mode select */
      uint8_t  AUTOEN                   :  1; /*!< Bias Enable mode */
      uint8_t  ATTEN                    :  1; /*!< ADC input Attenuation setting */
      uint8_t  SAMPCYC                  :  3; /*!< Sample cycle */
      uint8_t                           :  1; /*   (reserved) */
      uint8_t  ADCON                    :  8; /*!< ADC Status */
      uint16_t                          : 16; /*   (reserved) */
    };
    uint32_t WORD;
  } CONF; /* +0x000 */

  union {
    struct {
      uint8_t  CONVERT                  :  8; /*!< ADC START/STATUS Register */
      uint8_t  CONT                     :  1; /*!< Continuous Convesion Enable */
      uint8_t                           :  3; /*   (reserved) */
      uint8_t  DIVSEL                   :  2; /*!< Division factor select for the adc clock */
      uint8_t                           :  2; /*   (reserved) */
      uint16_t                          : 16; /*   (reserved) */
    };
    uint32_t WORD;
  } CNTRL; /* +0x004 */

  union {
    struct {
      union {
        struct {
          uint8_t  DATAREADY            : 1;
          uint8_t                       : 7;
        };
        uint8_t BYTE;
      } ENABLE;
      union {
        struct {
          uint8_t  DATAREADY            : 1;
          uint8_t                       : 7;
        };
        uint8_t BYTE;
      } CLEAR;
      union {
        struct {
          uint8_t  DATAREADY            : 1;
          uint8_t                       : 7;
        };
        uint8_t BYTE;
      } STATUS;
      union {
        struct {
          uint8_t  DATAREADY            : 1;
          uint8_t                       : 7;
        };
        uint8_t BYTE;
      } IRQ;
    };
    uint32_t WORD;
  } ADCIRQ; /* +0x008 */

  union {
    struct {
      uint8_t  CH0                      :  5; /*!< INSEL0 */
      uint8_t                           :  2; /*   (reserved) */
      uint8_t  SYNCENA0                 :  1; /*!< Sync Enable for Channel0 */
      uint8_t  CH1                      :  5; /*!< INSEL1 */
      uint8_t                           :  2; /*   (reserved) */
      uint8_t  SYNCENA1                 :  1; /*!< Sync Enable for Channel1 */
      uint8_t  CH2                      :  5; /*!< INSEL2 */
      uint8_t                           :  2; /*   (reserved) */
      uint8_t  SYNCENA2                 :  1; /*!< Sync Enable for Channel2 */
      uint8_t  SEQ                      :  2; /*!< Number of Channels for Sequencing */
      uint8_t                           :  2; /*   (reserved) */
      uint8_t  GUARD                    :  1; /*!< GUARD for ADC input Mux Switching */
      uint8_t                           :  3; /*   (reserved) */
    };
    uint32_t WORD;
  } INSEL; /* +0x00C */

  uint16_t DATA0;                             /* +0x010 */
  uint8_t  _RESERVED_12[2];                   /* +0x012 */

  uint16_t DATA1;                             /* +0x014 */
  uint8_t  _RESERVED_16[2];                   /* +0x016 */

  uint16_t DATA2;                             /* +0x018 */
  uint8_t  _RESERVED_1A[2];                   /* +0x01A */

  uint32_t PWMSYNC0;                          /*<! PWM Sync Value for channel0 in the sequence +0x01C */

  uint32_t PWMSYNC1;                          /*<! PWM Sync Value for channel1 in the sequence +0x020 */

  uint32_t PWMSYNC2;                          /*<! PWM Sync Value for channel2 in the sequence +0x024 */

} ADC_SFRS_t;

/* --------  End of section using anonymous unions and disabling warnings  -------- */
#if   defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/**
 * @brief The starting address of ADC SFRS.
 */
#define ADC_SFRS ((__IO ADC_SFRS_t *)0x50010600)

#endif /* end of __ADC_SFR_H__ section */


